MMI IC Design Tools

SUE SoC Design Manager

Manage Your Design with SUE

Everything Needed to Manage Today's SoC Design Flow


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Manage your SoC Design with SUE

SUE combines schematic capture and verification with control of Verilog blocks, timing models, standard cell libraries and documentation. SUE is useful from an architectural level to plan your design, and manage the design process.

• Provides an architectural overview of your design.
• Fully hierarchical, SUE can drill down to gate-level or transistor level detail of any block.

An example DPC-SUE Design Flow for synthesis, timing and place-and-route
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• Structural Verilog is imported and automatically arranged as a schematic.
• Enter your designs quickly with the simple graphical user interface.

Here, a sample MMI Tools 3D Design Flow, seamlessly integrated with other point tools you already use
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MMI's DPC incorporates SUE SoC Design Manager

SUE Features

• Draw, view and edit schematics, icons, graphics and text
• Automatically:
  • Attach Verilog models and documentation to schematics
  • Generate Verilog from schematic symbols and vice versa
  • Generate layout when used with MAX-LS Layout Syhstem
• Highlight nets and cross-probe between layout and schematic
• Maintain multiple views (behavioral, RTL, structural) of all schematics
• Interactive cross-probing during simulation on schematic or waveform tool
• Includes waveform viewer
• Reads/writes OVI-compliant Verilog files
• No vendor lock-in from proprietary file formats or encryption. ASCII database for portability
• Standard netlist and simulator interfaces
• Complete Tcl/Tk programming interface and API