MAX-3D TSV Placer automatically finds "holes" for TSVs, and then automatically optimizes and places the TSVs.
TSV Placer shows 3D connectivity with flylines, and exports the TSV data back into your 2D tools.
The following examples illustrate a few of MAX-3D TSV Placer capabilities:
Video demonstration: (50 s)
In this real-time example, TSV Placer is run on a layout, resulting in all TSVs being positioned on the outside edges. Modifying the position of two chips, then re-running TSV placer, you notice the TSVs are now placed in a row in the center.
In the following video clip, blocks are placed on 3 stacked die, with connectivity shown via fly-lines. A simple menu-click automatically places the TSVs for all three die at once.
Video demonstration: (50 s)
3D floorplan: Connectivity for 3 stacked die; automatic TSV placement with demonstration of a blocking region leading to TSV shift, and routed connections.
The real-time video clip, below, demonstrates automatic placement of TSVs on a design with three chip levels.
The first image, a view of "before-and-after", clearly shows the TSV placement for 2 chip levels.
The second image is the three-dimensional view of the TSV placement. All Micro Magic tools provide this 3D layout view.
In a more complex example of placement, this video illustrates the flylines and subsequent auto-placement of TSVs
Video demonstration: (33 s)
Blocks on 3 stacked die with connectivity fly-lines; subsequent menu-click for TSV placement, displayed in 3D.
MAX-3D TSV Placer, along with MAX-3D Path Finder and MAX-3D System, offer a comprehensive means of successfully designing, testing and producing today's complex three-dimensional TSV layouts.
MAX-3D TSV Placer is part of Micro Magic's 3D Design Suite together with MAX-3D System and MAX-3D Path Finder
“Tezzaron has taped out over 100 3D chips using MMI’s MAX-3D tool suite. There’s nothing to compare, and the new TSV placer & MAX-3D Path Finder are incredible.”
Robert Patti, VP/CTO, Tezzaron Semiconductor
“This is one of the few tools that can deal with multiple levels of hierarchy and multiple tech files all at the same time, and it is awesome for visualization of complex things like, say, PDN mesh across multiple die and interposers. Fantastic! I like it!”
Riko Radojcic, Director of Design for Silicon Initiatives, Qualcomm